For some nets, the net labels are used and for other the port names are used in the final PCB netlist even though both net labels and port names are assigned.Īltium cannot use a multi-part component in the multiple instances. The rule for flattening the netlist seems applied inconsistently. If we try to connect nets by name, we find Altium actually consider the net with net label and the net connect to the port with the same name to be different in PCB while showing exactly the same name. There does not seem to have a well defined way of resolving net names.Īnother thing that could cause confusion is the netlist option 'Allow Ports to Name Nets'. Altium would even complain about same net names in different hierarchy. More confusion is created when the nets are flatten: what net names are ultimately used if nets are assigned names in the hierarchy. If we think of ports are module interface declaration, inside the module, the port name should be used as signal names. The ports are considered differently from the wires so the port names do not become signal names even when the wires are not named.

We are forced to define unique names to different sheets. In a true hierarchical design, the local nets should stay local, but Altium seems to have problems with sheets with same named local nets. Those concepts have long been prevalent in software design. It can help manage large designs and encourage design reuse. Altium Designer promotes hierarchical design, which seems to make sense.

Altium hierarchical design